The present invention relates to a two-dimensional physical quantity detecting apparatus for detecting a physical quantity distribution of electromagnetic waves including visible or invisible light, particle radiations such as alpha rays or beta rays, and more particularly, it relates to a solid state imaging device and a solid state imaging system including sensing elements such as photoelectric conversion elements arranged in the form of a matrix and an AD conversion circuit for receiving an output signal from the sensing elements.
In addition to a CCD (charge coupled device) type sensor (hereinafter referred to as a “CCD sensor”) conventionally mainly used as an image sensor, a MOS type image sensor (hereinafter referred to as a “MOS sensor”) utilizing standard process technology for a logic LSI is widely commercially available in these days. As a characteristic of a MOS sensor, a variety of analog circuits and digital circuits can be integrated on the same substrate as a pixel array, which is different from a CCD sensor. In using a CCD sensor, a digital output can be obtained only by using additional chip having an AD conversion function, such as an analog front end processor (AFE) specialized in an analog signal amplification function and an AD conversion function, or a digital signal processor (DSP) having the function of an AFE, is connected to the CCD sensor output. In contrast, a MOS sensor in which an AD conversion circuit and a pixel array are together integrated on the same chip has been already commercialized.
For an AD conversion circuit included in a MOS sensor, various conversion systems including a pipeline AD conversion system widely employed in an AFE, a column AD conversion system for AD converting pixel data of one line simultaneously in parallel and a system for AD converting all pixel data simultaneously in parallel have been proposed. With respect to the column AD conversion system, various architectures have been proposed in, for example, Japanese Laid-Open Patent Publication No. 2005-347931, U.S. Pat. No. 5,877,715 and Japanese Laid-Open Patent Publication No. 2005-323331.
FIG. 16 is a diagram for showing the architecture of a MOS sensor according to Conventional Example 1 disclosed in Japanese Laid-Open Patent Publication No. 2005-347931.
The MOS sensor of Conventional Example 1 includes a column AD conversion circuit 1106 including a comparator 1107 and a digital memory 1108 corresponding to each column of pixels 1101. A binary value output from a binary counter 1104 is input to a DA conversion circuit (hereinafter referred to as the DAC) 1105. The DAC 1105 generates an analog ramp voltage (triangle wave) 1122 according to the input binary value and outputs the analog ramp voltage 1122 to the comparator 1107 as a reference potential. The output of the binary counter 1104 is also input to a binary/Gray code converter 1115 to be converted into a Gray code, which is distributed to the digital memories 1108 of all the columns. A pixel signal is input from the pixel 1101 through a read signal line 1103 to another input port of the comparator 1107 of each column AD conversion circuit 1106.
Next, the AD conversion operation of the MOS sensor of Comparative Example 1 will be described. First, in synchronization with a clock signal 1121 input from a clock generation circuit 1120, the binary counter 1104 starts counting from the initial value and at the same time, the DAC 1105 starts generating the analog ramp voltage 1122. Then, a signal read from the pixel 1101 of each column and the common analog ramp voltage 1122 varied in synchronization with a counter value of the binary counter 1104 are input to the comparator 1107 of each column. In parallel, the counter value of the binary counter 1104 is converted into a Gray code counter value 1124 by the binary/Gray code converter 1115 so as to be distributed to the digital memories 1108. When the relationship in amplitude between the two input signals to the comparator 1107 of a given column is changed, the output signal of this comparator 1107 is inverted, and the digital memory 1108 of this column holds the Gray code counter value 1124 output from the binary/Gray code converter 1115. Since the analog ramp voltage 1122 input to the comparator 1107 and the Gray code counter value 1124 input to the digital memory 1108 are synchronized with each other through the binary counter 1104, the read signal (i.e., an analog signal) from the pixel is AD converted into the value held by the digital memory (i.e., a digital signal) through this operation.
In this manner, in the MOS sensor according to Conventional Example 1 disclosed in Japanese Laid-Open Patent Publication No. 2005-347931, a Gray code is employed as a method for expressing a digital value supplied to a digital memory. Therefore, the Gray code counter value 1124 always changes with the minimum Hamming distance of “1”, and hence, even when skew is caused between bits distributed as a clock, a sampling error can be reduced. Furthermore, in successive counter values of the Gray code, merely one of the all bits is inverted, and hence, noise is suppressed. Moreover, power consumption can be reduced.
FIG. 17 is a diagram for showing the common concept of the architecture of a MOS sensor according to Conventional Example 2 disclosed in U.S. Pat. No. 5,877,715 and Japanese Laid-Open Patent Publication No. 2005-323331. The architecture of the MOS sensor according to Conventional Example 2 including another type of column AD conversion circuit will be described with reference to this drawing.
The MOS sensor according to Conventional Example 2 includes a column AD conversion circuit 1106 including a comparator 1107 and a column counter 1208 corresponding to each column of pixels 1101. A clock generation circuit 1120 supplies a clock signal 1121 not only to a binary counter 1104 but also to the column counter 1208 included in the column AD conversion circuit 1106. A binary value output from the binary counter 1104 is input to a DA conversion circuit (DAC) 1105, and the DAC 1105 generates an analog ramp voltage (triangle wave) 1122 in accordance with the input binary value. The analog ramp voltage 1122 is input to the comparator 1107 as a reference potential. A pixel signal is input from the pixel 1101 through a read signal line 1103 to another input port of the comparator 1107.
In the MOS sensor of Conventional Example 2 shown in FIG. 17, signals supplied to an array of the column AD conversion circuits to generate a resultant digital value are reduced to a single clock signal 1121 generated by the clock generation circuit 1120.
Next, the AD conversion operation of the MOS sensor of Conventional Example 2 will be described.
First, the column counter 1208 included in the column AD conversion circuit 1106 and the binary counter 1104 are initialized in accordance with an initialization signal (not shown), and an initial value of the analog ramp voltage 1122 is supplied from the DAC 1105 to one input port of the comparator 1107. Next, a pixel signal is read from a pixel 1101 of a selected row to be supplied to the other input port of the comparator 1107. After that, the clock signal 1121 is started to be input to the binary counter 1104 and the column counter 1208, so that the binary counter 1104 can start counting from the initial value. Then, the DAC 1105 also starts generating the analog ramp voltage 1122 from the initial value in accordance with the counter value of the binary counter 1104. Also, the column counter 1208 included in the column AD conversion circuit 1106 starts counting clock signals 1121 input thereto.
Subsequently, when the relationship in amplitude between the two signals input to the comparator 1107 of a given column is changed and the output signal of this comparator 1107 is inverted, the clock signal 1121 to be input to the column counter 1208 of this column is masked, and hence, the column counter 1208 holds a current counter value. Since the analog ramp voltage 1122 and the counter value of the column counter 1208 are synchronized with each other in accordance with the clock signal 1121, the read signal from the pixel (i.e., an analog signal) is AD converted into the value held by the digital memory (i.e., a digital signal) through this operation.
The aforementioned two AD conversion systems are of a kind of the column AD conversion system designated as ramp run-up ADC, and in accordance with general classification of AD conversion, these systems are designated as counting ADC. These systems are thus designated because the use of a triangle wave as a reference potential is equivalent to conversion of an analog signal potential of a pixel into a time length and the time length is measured by using a clock signal of a certain fixed frequency for the AD conversion.
The AD conversion of 10 bits, for example, requires to count the number of tones of 10 bits (namely, 1024) in comparing a signal obtained from a pixel with a reference potential (an analog ramp voltage) generated by a DAC. In the case where merely one signal is obtained from the pixel to be AD-converted at a time, the AD conversion can be completed when the relationship in amplitude between the signal potential and the reference potential is inverted, and there is no need to perform further comparison. However, in the case where pixels of, for example, one row are subjected to the AD conversion in parallel as in an AD conversion circuit included in a MOS sensor, it cannot be confirmed whether or not the conversion has been completed with respect to all the pixels by a general architecture, and therefore, the comparison should be performed 1024 times after all.
At this point, a camera provided in a cellular phone is assumed as a specific exemplified product. Even cellular phones have recently employed the mega class number of pixels and need specifications of, for example, five million pixels and a frame rate of 15 frames/sec.
For the sake of simplification, it is assumed that the aspect ratio of a pixel array of five million pixels is 2000 rows by 2500 columns, and for further simplification, it is assumed that there is no blanking period. In this case, a reading period for one row is 15 frames/sec×2000 rows/frame=30 Kline/sec. In other words, the reading rate for one row is 30 KHz.
When the “ramp run-up ADC” is applied to this product, it is necessary to perform, for 10-bit AD conversion, the comparison the number of times corresponding to the number of tones, that is, 210=1024 times, in the reading period for one row. Thus, it is necessary to change the counter value of a counter to be output to a digital memory at a rate approximately 1000 times as large as the reading rate for one row, namely, approximately 30 MHz.
In this calculation, no consideration is paid to periods when the comparison for the AD conversion cannot be performed, namely, a waiting period in which the AD conversion circuit receives data from the pixels and a transfer time in which the result of the AD conversion is transferred to an output memory. Furthermore, apart from the above-described number of pixels, an OB (optical black) pixel period and a blanking period are not considered. Therefore, the actual frequency is higher than the above estimated frequency (and is, for example, approximately 50 MHz).